1. Field of Invention
The present invention relates to a voltage regulator in semiconductor memory. More particularly, the present invention relates to a voltage down converter in dynamic random access memory (DRAM).
2. Description of Related Art
Along with the rapid development of science and technology at the present, semiconductor memories, as major storage devices for large amount of data are being developed to have larger and larger capacity. As the semiconductor technology is continuously scaled down to achieve high memory density, on-chip voltage regulators providing lower supply voltage for internal circuits are required to fulfill the requirements for high device reliability and low power consumption. For DRAM, the bit line sensing, restoring and pre-charge operations in the memory cell arrays consume current abruptly and heavily. For high density DRAM chip, it is challenging to design on-chip voltage regulators for memory cell arrays providing a stable voltage level (Vsa) with sufficient and appropriate supplying current.
FIG. 1 is a circuit diagram of a conventional voltage regulator 100 for DRAM. The voltage regulator 100 includes a differential amplifier unit 11 as a comparator, a feedback unit 12, a PMOS driver transistor mp11, and a NMOS transistor 13.
The differential amplifier unit 11 includes a plurality of transistors 111˜115. NMOS transistor 112 is connected in series with PMOS transistor 114. NMOS transistor 113 is connected in series with PMOS transistor 115. NMOS transistor 111 has its drain connected to the sources of both NMOS transistors 112 and 113, and its source connected to GND. The NMOS transistor 111, which gate is connected to a voltage Vbias1, provides a constant bias current for the differential amplifier unit 11. The NMOS transistor 112 detects Vfb1 from the feedback unit 12 and NMOS transistor 113 receives a reference voltage Vref1. The PMOS transistors 114 and 115, whose gates are connected together, constitute a current mirror. The PMOS transistor 114 has its gate and drain connected together and its source connected to a power supply Vdd. The PMOS transistor 115 is connected between the power supply Vdd and an output node of the differential amplifier unit 11. The PMOS driver transistor mp11, whose gate is connected to the output node of the differential amplifier unit 11, controls currents supplied from the power supply Vdd to the Vsa1 for internal circuits (not shown). The feedback unit 12, having resistors R11 and R12, adjusts the ratio of Vsa1 to the reference voltage Vref1. The feedback output voltage Vfb1 is equal to Vsa1*R12/(R11+R12). NMOS transistor 13, normally turned off, is turned on by a rising trigger signal tr1 to pull the gate voltage of PMOS driver transistor mp11 toward ground (GND) and supplies more current to Vsa1.
In operation, the differential amplifier unit 11 compares the feedback voltage Vfb1 with the reference voltage Vref1, and then applies the output signal to the gate of PMOS driver transistor mp11 to control the current and to regulate the internal power supply Vsa1 for DRAM cell array. If Vsa1 is lower and Vfb1 is less than Vref1, the gate of PMOS driver transistor mp11 will attain toward ground to raise Vsa1. While Vsa1 is getting higher, Vfb1 is rising toward Vref1 and the gate of PMOS driver transistor mp11 will attain toward Vdd to turn off PMOS driver transistor mp11 and stop the Vsa1 rising. In steady state, Vfb1 is equal to Vref1 and Vsa1 is regulated at Vref1*(R11+R12)/R12.
To prevent the excessive drop-down of Vsa1 during bit line sensing, which degrades the DRAM performance, the NMOS transistor 13, turned on and controlled by a trigger signal tr1, pulls down the gate voltage of PMOS driver transistor mp11 toward GND to supply more current and to raise the Vsa1 level in advance. This “reset” action prevents some excessive drop-down of Vsa1 voltage at bit line sensing afterwards. Due to lack of feedback from Vsa1 in controlling the “reset” and duo to slow response of the differential amplifier unit 11, Vsa1 is easier to be raised and dropped excessively.
The circuit in FIG. 1 has some drawbacks. Because there is no feedback from Vsa1 to control the turn-on “H” duration tr1 before large current consumption in Vsa1, Vsa1 may be pulled too high in case of high Vdd. Further, Tr1 goes low after large current consumption in Vsa1; and Vsa1 may be pulled too high or too low if the differential amplifier unit 11 responds slowly.
FIG. 2 shows another prior voltage regulator 200. The voltage regulator 200 includes a comparing unit 21, PMOS driver transistors mp21 and mp22, a feedback unit 22, a control unit 23 and switches 24 and 25. The comparing unit 21, as a differential amplifier, includes NMOS transistors 211˜213 and PMOS transistors 214-215. The comparing unit 21 differentiates a first signal from the feedback unit 22 with a voltage reference Vref2 to output a large swing amplifying signal S1 and a smaller swing complementary amplifying signal S2. The NMOS transistor 211 receives a gate voltage Vbias2 and supplies a biasing current for the comparing unit 21. Signal S1 controls the PMOS drive transistor mp21 to output an internal supply voltage Vsa2 for DRAM memory cells. The smaller swing complementary amplifying signal S2, output from the drain of the diode-connected PMOS transistor 214, controls the control unit 23. The feedback unit 22, including resistors R21 and R22, receives Vsa2 and generates a feedback signal Vfb2, based on the impedance ratio of R21 to R22, to an input of the comparing unit 21. The PMOS driver transistor mp21 provides a first control path to the internal supply voltage Vsa2 and the PMOS driver transistor mp22 provides a second control path to the internal supply voltage Vsa2. The control unit 23, including a PMOS transistor 231, is coupled to the comparing unit 21. The control unit 23 receives the smaller swing complementary amplifying signal S2 to output a control voltage V1 to the gate of the PMOS driver transistor mp22. The switch 24, including a PMOS transistor 241, is coupled to the PMOS driver transistor mp22 and receives a trigger signal tr2 for raising the control voltage V1 toward the power supply voltage Vdd. The switch 25, including an NMOS transistor 251, is also coupled to the PMOS driver transistor mp22 and receives the trigger signal tr2 to drop the control voltage V1 toward the ground voltage.
In normal operation without abrupt change in current consumption, Vsa2 is regulated at Vref2*(R21+R22)/R22 by the comparing unit 21, the PMOS driver transistor mp21 and the feedback unit 22. The output signal S1 of the comparing unit 21 is biased at a certain level such that the PMOS driver transistor mp22 just supplies the quiescent Vsa2 standby current. The complementary amplifying signal S2, which is the gate bias of the current mirror PMOS transistors 214-215, sets the gate bias of the PMOS transistor 231. The control voltage V1 input to the gate of the PMOS drive transistor mp22 is set at VDD until the trigger signal tr2 is rising.
Prepared for abrupt current consumption during the bit line sensing, the NMOS transistor 251, turned on by a rising trigger signal tr2, pulls down the gate voltage V1 of the second PMOS driver transistor mp22 to raises the internal supply voltage Vsa2 in advance. This “reset” action prevents the excessive drop-down of the internal supply voltage Vsa2. The PMOS transistor 231, which is controlled by the complementary amplifying signal S2 from the comparing unit 21, holds the control voltage V1 and restrains reset on the internal supply voltage Vsa2. After reset, a falling trigger signal tr2 turns-off the NMOS transistor 251 and turns on the PMOS transistor 241, raises the control voltage V1 to VDD to shut off the PMOS driver transistor mp22.
However, in the structure of FIG. 2, the comparing unit 21 is also of slow response because the bias current thereof is only provided by the NMOS transistor 211. Further, at the beginning of bit line sensing, currents provided by the PMOS driver transistor mp22 to Vsa2 may be not enough.
FIG. 3 is a timing chart of the voltage regulator 200 illustrated in FIG. 2. The horizontal axis represents the time, and the vertical axis represents the voltage. Before bit line sensing operation, Vsa2 is reset.
In U.S. Pat. No. 6,195,298 B2, another voltage down converter for supplying a voltage and current to semiconductor devices is provided. However, the voltage down converter, having three amplifiers, is more complex and has higher manufacturing cost.